1. Field of the Invention
The present invention relates to an information processing system and a control method of the same.
2. Description of Related Art
FIG. 8 shows a block configuration of an information processing system 1 that is connected using an SRAM interface bus. Referring to FIG. 8, the information processing system 1 includes a master LSI 10, a slave LSI 20, ROM 30, and an SRAM interface bus 40.
The master LSI 10, the slave LSI 20 and the ROM 30 are connected to the SRAM interface bus 40. The SRAM interface bus 40 is an AD-mux SRAM interface bus in which an address signal and a data signal are transmitted through a common bus line. Various control signals, the address signal and the data signal in conformity with the AD-mux SRAM interface protocol are transmitted through the SRAM interface bus 40. Specifically, in the SRAM interface bus 40, it is inhibited that the address signal and the data signal are transmitted simultaneously.
The master LSI 10 controls the slave LSI 20 and the ROM 30. The master LSI 10 accesses the slave LSI 20 or the ROM 30 through the SRAM interface bus 40, and it can read data held by the slave LSI 20 or the ROM 30 or write data to the slave LSI 20 or the ROM 30.
For example, in the case of reading data held by the slave LSI 20 (which is referred to hereinafter as a read command), the master LSI 10 outputs an address signal ADDR and an activated address valid signal ADVB to the slave LSI 20 through the SRAM interface bus 40. After that, the master LSI 10 activates an output enable signal OEB and reads data corresponding to the address signal ADDR which is latched by the slave LSI 20 through the SRAM interface bus 40.
Further, in the case of writing data to the slave LSI 20 (which is referred to hereinafter as a write command), the master LSI 10 outputs an address signal ADDR and an activated address valid signal ADVB to the slave LSI 20. After that, the master LSI 10 activates a write enable signal WEB and outputs write data to the SRAM interface bus 40 corresponding to the address signal ADDR which is latched by the slave LSI 20.
Note that, in the case of reading data held by the ROM 30 also, the master LSI 10 performs basically the same operation as in the case of reading data held by the slave LSI 20.
Further, RAM 11 is connected externally to the master LSI 10. The master LSI 10 and the RAM 11 are connected through a DDR bus, for example. In the RAM 11, a memory address space which is managed by the master LSI 10 is mapped. Further, a peripheral LSI 12 is connected to the master LSI 10. The peripheral LSI 12 and the master LSI 10 are connected through a serial bus, for example.
In the ROM 30, programs, data or the like to be processed by the master LSI 10 are stored. The ROM 30 is accessed by the master LSI 10 through the SRAM interface bus 40, reads data or the like stored therein, and outputs the read data to the master LSI 10. For example, the ROM 30 receives an address signal ADDR and an activated address valid signal ADVB from the master LSI 110 and latches the value of the address signal ADDR. After that, the ROM 30 receives an activated output enable signal OEB, reads data corresponding to the value of the latched address signal ADDR, and outputs the read data to the SRAM interface bus 40. The ROM 30 is made of NOR flash memory, pseudo-SRAM or the like.
The slave LSI 20 is a processor that performs prescribed processing in response to a command from the master LSI 10, and it implements a part of the functions of the information processing system 1, such as communication protocol control or image processing, for example. The slave LSI 20 is under control of the master LSI 10. Then, by an access from the master LSI 10, the slave LSI 20 reads memory data under the slave LSI 20, which is described later, and sends the read data back, or writes write data from the master LSI 10 as memory data under the slave LSI 20.
Further, the slave LSI 20 includes a bus converter 21, a direct memory access circuit (DMA) 22, a processor 23, a memory controller (MEMC) 24, a peripheral circuit 25, and an internal bus 26. Furthermore, RAM 27 is connected externally to the slave LSI 20. The memory controller 24 is connected to the RAM 27 through a DDR bus, for example. The slave LSI 20 has an internal memory space, and the internal memory space includes a memory address space in the RAM 27 and a memory address space allocated to each circuit inside the slave LSI 20 such as the peripheral circuit 25 or a register. Hereinafter, data read from the internal memory space or data written to the internal memory space is referred to as memory data under the slave LSI 20.
The bus converter 21 performs protocol conversion that converts various kinds of signals from the SRAM interface bus 40 into signals conforming to the internal bus 26 of the slave LSI 20 or, reversely, converts various kinds of signals from the internal bus 26 into signals conforming to the SRAM interface bus 40. Further, the bus converter 21 may include a buffer that temporarily stores the value of the address signal or the value of the write data signal which is transmitted from the SRAM interface bus 40, a prefetch buffer that previously reads and stores data of the subsequent address on the basis of the value of the stored address signal or the like.
When a burst access is required for read data, for example, the direct memory access circuit (DMA) 22 reads the requested consecutive data from the RAM 27. The processor 23 controls the respective circuits of the slave LSI 20 and performs various kinds of requested processing operations. The memory controller 24 performs data reading, writing, refresh operation or the like on the RAM 27 connected thereto. The peripheral circuit 25 is a timer or the like, for example.
FIGS. 9 and 10 show timing charts to explain the internal operation of the slave LSI 20 of the information processing system 1 described above. First, FIG. 9 is a timing chart to explain the operation in which memory data under the slave LSI 20 is read by an access from the master LSI 10. Note that an external clock signal CLK, a chip select signal CSB, an address valid signal ADVB, an output enable signal OEB and a write enable signal WEB are output from the master LSI 10 and received by the slave LSI 20 through the SRAM interface bus 40. It is assumed that those signals are negative logic signals.
The external clock signal CLK for synchronous access is an operating clock of the bus converter 21. The chip select signal CSB is a signal for controlling a standby mode and a normal operation mode of the bus converter 21. The address valid signal ADVB is a signal for controlling the timing when the slave LSI 20 latches the address signal transmitted through the SRAM interface bus 40. The output enable signal OEB is a signal for controlling a data read operation on the slave LSI 20. The write enable signal WEB is a signal for controlling a data write operation on the slave LSI 20.
Further, a wait signal WAITB is output from the bus converter 21 and received by the master LSI 10 through the SRAM interface bus 40. It is also assumed that the wait signal WAITB is a negative logic signal. The wait signal WAITB is a signal for notifying the master LSI 10 that the slave LSI 20 is in a busy state.
Referring to FIG. 9, at time t1, the chip select signal CSB and the address valid signal ADVB from the master LSI 10 fall to the low level at the same time, for example. Further, the address signal ADDR that is output from the master LSI 10 is transmitted through the SRAM interface bus 40.
Because the chip select signal CSB falls to the low level at the time t1, the bus converter 21 changes from the standby mode to the normal operation mode. Then, at time t2, the external clock signal CLK rises. Because the address valid signal ADVB is the low level at this time, in synchronization with the rising edge of the external clock signal CLK, the bus converter 21 latches the address signal ADDR. The value of the latched address signal is stored into the buffer of the bus converter 21.
At time t3, the address valid signal ADVB rises. At the same time, the slave LSI 20 outputs the low-level wait signal WAITB to the master LSI 10.
At time t4, the output enable signal OEB falls. When the bus converter 21 receives the low-level output enable signal OEB, it determines that an access from the master LSI 10 is a read command, and the slave LSI 20 starts the read operation for reading memory data under the slave LSI 20 in accordance with the value of the latched address signal. Note that the memory data under the slave LSI 20 which is read by the slave LSI 20 includes register data generated or stored in the peripheral circuit 25, data stored in the external RAM 27 under control of the slave LSI 20 or the like.
Then, from time t5, the slave LSI 20 performs the read operation of the above-described memory data under the slave LSI 20. Assume that the read operation requires an internal access time Tacs which corresponds to four clocks of the external clock signal CLK. The internal access time Tacs includes various operation processing time inside the slave LSI 20, such as processing time to convert various signals from the SRAM interface bus 40 into signals conforming to the internal bus 26 of the slave LSI 20, time for the bus converter 21 to access the peripheral circuit 25 or the external RAM 27 through the internal bus 26, or time for an access issued by the bus converter 21 and an access issued by the processor 23 or the DMA 22 to contend in the internal bus 26 and wait, for example.
At time t6, which is after the lapse of the internal access time Tacs from the time t5, the read operation of the memory data under the slave LSI 20 is completed, and the wait signal WAITB rises. Then, at time t7, in synchronization with the rising edge of the external clock signal CLK, read data DATA1 is output from the bus converter 21 to the SRAM interface bus 40. Note that, when the read data is a burst access, read data DATA2 is output to the SRAM interface bus 40 continuously at time t8. Although only DATA1 and DATA2 are shown in FIG. 9, more read data may be output continuously.
Finally, at time t9, the output enable signal OEB and the chip select signal CSB rise to the high level at the same time, for example. The chip select signal CSB thereby becomes the high level, the bus converter 21 enters the standby mode, and a series of operations to read the memory data under the slave LSI 20 by an access from the master LSI 10 ends. Note that, in FIG. 9, the write enable signal WEB is always at the high level.
FIG. 10 is a timing chart to explain the operation in which write data DATA 1 and write data DATA2 are written to memory data under the slave LSI 20 by an access from the master LSI 10. Note that the operation up to time t3 is the same as that of FIG. 9 and explanation thereof is omitted. However, when the bus converter 21 latches the address signal ADDR at the time t3, it sets the wait signal WAITB to the low level for a predetermined period from the latch operation.
At time t4, the write enable signal WEB falls. When the bus converter 21 receives the low-level write enable signal WEB, it determines that an access from the master LSI 10 is a write command, and the slave LSI 20 starts the write operation for writing write data into memory data under the slave LSI 20 in accordance with the value of the latched address signal. However, because the write data is not output from the master LSI 10 at this point of time, the write operation is not performed, and it enters a write data waiting mode. Specifically, at the time t4, the bus converter 21 can only perform a determination operation that determines to perform the write operation.
Then, when the write data DATA1 is output from the master LSI 10, in synchronization with the rising edge of the external clock signal CLK, the bus converter 21 latches the write data DATA1 at time t5, and writes the write data into the internal address space. Note that, when the write data is a burst access, the bus converter 21 latches write data DATA2 continuously at time t6 and then writes the write data into the internal address space.
At time t7, the write enable signal WEB and the chip select signal CSB rise to the high level at the same time, for example. Because the chip select signal CSB becomes the high level, the bus converter 21 enters the standby mode. After the subsequent time t8, an access inside the slave LSI 20 is started, and the write data DATA1 and DATA2 are written into the memory data under the slave LSI 20 in accordance with the value of the latched address signal. Note that, in the write operation in FIG. 10, the output enable signal OEB is always at the high level.
The timing charts similar to the above-described timing charts of FIGS. 9 and 10 are disclosed in “Numonyx StrataFlash Cellular Memory (M18-90nm/65nm)”, Numonyx, Jun. 2009, and “Mobile FRCAM data sheet for MB82DBS04164E-70L”, FUJITSU MICROELECTRONICS LIMITED, 2008-2009, respectively.